I. Field of the Disclosure
The present disclosure generally relates to context switch, such as methods of switching among normal, shadow and test contexts.
II. Description of the Related Art
Advances in technology have resulted in smaller and more powerful personal computing devices. For example, a variety of portable personal computing devices, including wireless computing devices, such as portable wireless telephones, personal digital assistants (PDAs), and paging devices are small, lightweight, and easily carried by users. More specifically, portable wireless telephones, such as cellular (analog and digital) telephones and IP telephones, can communicate voice and data packets over wireless networks. Further, many such wireless telephones include other types of devices that are incorporated therein. For example, a wireless telephone can also include a digital still camera, a digital video camera, a digital recorder, and an audio file player. Also, such wireless telephones can include a web interface that can be used to access the Internet. As such, these wireless telephones include significant computing capabilities.
To provide multiple functions, such portable personal computing devices often include a multi-processing system, such as a multi-threaded processor (e.g. a processor capable of handling more than one program or process at a time. In a multi-threaded processing system, the operating system shares the processor among various threads (processes). Threads (processes) are constructed by the operating system. This sharing is typically implementing by switching between processes, where each process represents a context.
In general, a multi-threaded processing system generally has a register file that may include an array of register cells. Each register cell typically includes an output multiplexer to select between contexts (processes), which may be provided to a multiplexer for the array of register cells to select, for example, among sets/rows of data within the register file. In this instance, context switch is implemented by controlling the output multiplexer of each cell to provide the selected context to the multiplexer for the array of register cells. In a particular example, a register may be a logic latch-based storage register or a static random access memory (SRAM) based storage register. The output multiplexer of each storage register cell is fed into another output multiplexer for the entire register cell array.
With advances in semiconductor fabrication technologies, integrated circuit devices, such as processors, have decreased in size, and the density and complexity of such integrated circuits has increased. This greater circuit density has made testing more difficult and costly. Design-for-testability (DFT) refers to a technique for reducing the complexity associated with design testing by including test logic and access points for accessing such test logic within an integrated circuit device. Modern integrated circuits usually incorporate a variety of design-for-test (DFT) structures to enhance their inherent testability. Typically, the DFT structures are based on a scan design or an automatic test pattern generation (ATPG) design, where scan test or ATPG test data may be provided to a test pin or where a plurality of externally accessible scan chains may be embedded into the integrated circuit. Typically, scan test design is used in conjunction with fault simulation and combinational automatic test pattern generation (ATPG) to generate manufacturing and diagnostic test patterns for production test and prototype debug processes.
To provide DFT functionality, a circuit may have a test input, which can be accessed during a test mode and which may be tied to a logic level during normal non-test operation. A multiplexer may be introduced to select between testing and non-testing modes and to provide a data pattern to an array output multiplexer.
For static latch-based register files, such register cell-based output multiplexers are often utilized to select between normal or shadow context to provide two execution data contexts, such as a normal data context (current process) and a shadow data context (second process). To add a test capacity, an additional two-to-one multiplexer may be added to register latch's input for additional scan test data. For a static random access memory (SRAM) type of register file, a dual-port memory cell may be needed to support both the normal data context and the shadow data context. Moreover, for testability, additional logic may be needed to support a memory built-in self-test (MEM BIST). Such additional logic introduces undesirable delays in the normal and shadow data contexts access time.
Accordingly, it would be advantageous to provide an improved context switch mechanism and DFT (design-for-testability) capability for latch-based register files.